An integrated circuit (IC) device typically includes an IC chip that is housed in a plastic, ceramic or metal package. The IC chip typically includes a circuit fabricated by lithographically patterning conductive and insulating materials on a thin wafer of semiconductor using known fabrication techniques. The package supports and protects the IC chip and provides electrical connections between the circuit and an external circuit or system.
It is important to note that a design of an integrated circuit device cannot be verified by “bread-boarding” but must be simulated. Simulation of Integrated circuits is commonly implemented with a SPICE program (Simulation Program with Integrated Circuit Emphasis). There are many types and iterations of SPICE programs. However, they have the common requirement that circuit elements of the integrated circuit must be characterized and mathematically represented in the SPICE program netlist.
As ICs have gotten faster with smaller and smaller feature sizes, they have also gotten much more complex. Examples of complex IC devices include microprocessors, Application-Specific ICs (ASICs), and Programmable Logic Devices (PLDs) which are capable of implementing digital logic operations in digitally configured logical fabric, and many others. There are several types of PLDs, including Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs).
Modern, highly complex, ICs can and often do include hundreds of Input/Output structures and associated connection infrastructure, such as bonding pads for example, that access the device's logical circuitry. To support the large number of I/O structures, complex ICs are typically mounted in a package that includes multiple external contacts that can be, for example, pins, solder balls/bumps, or wire leads. Several package types are used to house IC chips, such as ball grid arrays (BGAs), pin grid arrays (PGAs), plastic leaded chip carriers, plastic quad flat packs and others, for example. The package type selected by an IC manufacturer for a particular IC chip is typically determined by the size/complexity of the IC chip (i.e., the number of input/output terminals), and the requirements of the chip's end use.
One type of an IC chip package is a “flip chip,” which does not require any wire bonds. Instead the final wafer processing step deposits solder beads on the chip pads. After cutting the wafer into individual dice, the “flip chip” is then mounted upside down in/on a package substrate which contains matching contact points and connections to the associated external circuitry. The solder is reflowed in order to bond the contacts of the chip and the substrate. Flip chips then normally undergo an under fill process which covers the sides of the die, similar to an encapsulation process.
FIG. 1 shows a side cross-sectional view of an exemplary packaged flip-chip BGA IC device 100 including flip chip 160, and package planes substrate 120. IC package 100 is electrically connected to contacts 159 on a printed circuit board (PCB) 130 through solder balls 140 that extend from contacts 126 on the lower surface of the package substrate 120 of the IC package 100. The PCB is electrically connected to package substrate 120 through conductive planes 127, 128, 129 and conductive vias 124. From the lower surface of the package substrate 120, a plurality of solder balls 140 extend to contact the contact pads 159 on the upper surface of printed circuit board 130. The package planes are also electrically connected to flip-chip 160 through conductive lines and conductive vias 124 making up conductive planes that are provided in the package substrate 120. From the upper surface of the package substrate 120, a plurality of solder bumps 110 extend to contact the contact pads 111 of the flip-chip 160. A cover, such as a cap or “glob top,” is placed or formed over flip-chip 160 and package substrate 120 into a single, relatively robust, unit for ease of handling and for protection.
Flip-chip BGA packages continue to evolve in terms of complexity, and on-die voltages continue to decrease with advances in deep sub-micron technology. Because the signals and voltages in package planes are large in comparison to the proximity of the IC components and the package planes, proximity effects take on more and more importance to the operation of the integrated circuit. Simulating these effects, such as power supply droop, ground bounce and crosstalk between adjacent signals, thus becomes more important in determining effective package component design.
In the past, a simple lumped inductor model was sufficient to model wirebond packages. In current flip-chip BGAs, however, dielectric layer counts can exceed ten layers where complex geometries define power planes and interconnections between signal vias and traces. However, current modeling for flip-chip BGAs requires use of expensive and complex software tools. These software tools are limited because they employ a finite element method analysis, and thus there are not enough elements available to adequately simulate current flip-chip BGAs. Further, these software tools require a lot of computing power for simulations. Still further, these software tools are time consuming, leaving engineers with very little time to analyze and address design concerns, and don't enable engineers to fully understand the impacts and effects of power supply droop, ground bounce and crosstalk between adjacent signals either at the package level or at the system level.